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1 fn6742.2 isl99201 filterless high effici ency 1.5w class d mono amplifier the isl99201 is a fully integrated high efficiency class-d mono amplifier. it is designed to maximize performance for mobile phone applications. the application circuit requires a minimum requirement of external components and operates from a 2.4v to 5.5v input supply. it is capable of delivering 1.4w of continuous output pow er with less than 1% thd+n driving a 8 ? load from a 5v supply. the isl99201 features a high-efficiency, low-noise modulation scheme. it operates with 86% efficiency at 400mw into 8 ? and has a signal-to-noise ratio (snr) that is better than 95db. the isl99201 has a micro-power shutdown mode with a typical shutdown current of 200na. shutdown is enabled by applying a logic low to the sd pin. the architecture of the devices allows it to achieve very low level of pop-and-click. this mini mizes voltage glitches at the output during turn-on and turn-off, thus reducing audible noise on activation and deactivation. the fully differential input of the isl99201 provides excellent rejection of common mode noise on the input typically 75db. emi suppression is achieved by src (slew rate control). the isl99201 oscillator can be synchronized to an external clock through the sync input, allowing the switching frequency to be externally defined. the sync input also allows multiple isl99201 to be cascaded and frequency locked; minimizing interference due to clock intermodulation. the isl99201 also has excellent rejection of power supply noise, including noise caused by gsm transmission bursts and rf rectification. psrr is typically 75db at 217hz. there will be 4 versions of the part; they will consist of three fixed gain settings (6db, 9. 6db, 12db) and one user programmable gain setting (need external resistors). the isl99201 has built-in thermal shutdown and output short-circuit protection. features ? filterless class d with efficiency > 86% at 400mw ? click-pop suppression ? slew rate control ? spread spectrum switching ? optional sync pin for master/slave operation without interface ? 1.4w into 8 ? with less than 1% thd+n ? 2.4v to 5.5v single supply voltage ? built-in resistors to reduce board component count ? only one external component required (fixed gain mode) ? short circuit and thermal protection ? gain programmable 6db, 9.6db, 12db and user programmable ? pb-free (rohs compliant) applications ? mobile phones ? mp3 players ? portable gaming ? portable electronics ? educational toys data sheet november 1, 2013 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2009, 2012, 2013. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
2 fn6742.2 november 1, 2013 pinout isl99201 (8 ld tdfn) top view ordering information part number part marking gain setting (db) temp. range (c) package tape and reel (pb-free) pkg. dwg. # isl99201irtaz-t (notes 1, 2) 201a 6 -40 to +85 8 ld 3x3 tdfn l8.3x3a isl99201irtaz-tk (notes 1, 2) 201a 6 -40 to +85 8 ld 3x3 tdfn l8.3x3a isl99201irtbz-t (notes 1, 2) 201b 9.6 -40 to +85 8 ld 3x3 tdfn l8.3x3a isl99201irtbz-tk (notes 1, 2) 201b 9.6 -40 to +85 8 ld 3x3 tdfn l8.3x3a isl99201irtcz-t (notes 1, 2) 201c 12 -40 to +85 8 ld 3x3 tdfn l8.3x3a isl99201irtcz-tk (notes 1, 2) 201c 12 -40 to +85 8 ld 3x3 tdfn l8.3x3a isl99201irtdz-t (notes 1, 2) 201d prog. -40 to +85 8 ld 3x3 tdfn l8.3x3a isl99201irtdz-tk (notes 1, 2) 201d prog. -40 to +85 8 ld 3x3 tdfn l8.3x3a ISL99201IRTAEVZ evaluation board isl99201irtbevz evaluation board isl99201irtcevz evaluation board isl99201irtdevz evaluation board notes: 1. please refer to tb347 or details on reel specifications. 2. these intersil pb-free plastic packaged pr oducts employ special pb-free material sets , molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-free peak reflow temperat ures that meet or exceed the pb-free requirements of ipc/jed ec j std-20. 2 3 4 1 7 6 5 8 sd sync in+ in- vo- gnd vdd vo+ isl99201 *
3 fn6742.2 november 1, 2013 absolute maximum ratings (ref erence to gnd) thermal information supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6v input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to v dd +0.3v recommended operating conditions ambient temperature range . . . . . . . . . . . . . . . . . . -40c to +85c operating supply voltage (vdd pin) . . . . . . . . . . . . . . 2.4v to 5.5v thermal resistance (typical note 3) ja (c/w) tdfn package . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 maximum junction temperature (plastic package) -65c to +150c maximum storage temperature range . . . . . . . . . -65c to +150c power dissipation ratings 8 ld 3x3 tdfn derating factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.8mw/c power ratings t a = +25c. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7w t a = +70c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7w t a = +85c. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4w pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed for extended periods of time. expos ure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. note: 3. ja is measured in free air with the component mounted on a high ef fective thermal conductivity test board with ?direct attach? fe atures. see tech brief tb379 electrical specifications typical values are tested at v dd = 5v and the ambient temperature at +25c. parameter symbol test conditions min (note 5) typ max (note 5) units output power p o r l = 8 , thd = 10%, f = 1khz, 20khz bw, v dd = 5.0v 1.4 w r l = 8 , thd = 10%, f = 1khz, 20khz bw, v dd = 3.6v 0.75 w r l = 8 , thd = 10%, f = 1khz, 20khz bw, v dd = 2.5v 0.4 w r l = 8 , thd = 1%, f = 1khz, 20khz bw, v dd = 5.0v 1.15 w efficiency p out = 1.4w, 8 + 33h, v dd = 5.0v 90 % total harmonic distortion + ratio thd+n p o = 1w into 8 each channel, f = 1khz, v dd = 5.0v 0.05 % p o = 0.5w into 8 each channel, f = 1khz, v dd = 3.6v 0.05 % p o = 0.2w into 8 each channel, f = 1khz, v dd = 3.6v 0.09 % common-mode rejection ratio cmrr v ic = 0.5v to (v dd - 0.8v); r l = 8 , v dd = 2.5v to 5.5v -60 db cmrr gsm v cm = 2.5v 1v p-p at 217hz, r l = 8 -60 db average switching frequency f sw v dd = 5v 300 375 450 khz differential output offset voltage v oos g = 6db; 9.6db; 12db; 28db. 0.2 5.0 mv power supply supply voltage range v dd 2.4 5.5 v power supply rejection ratio psrr v dd = 2.5v to 5.0v -65 db psrr gsm v ripplt = 100mv rms at 217hz (input ac-coupled with 2f capacitor) -65 db supply current i in v in = 0v, no load, v dd = 5v 3.9 ma v in = 0v, no load, v dd = 3.6v 3.2 3.75 ma v in = 0v, 8 + 33h, v dd = 5v 3.9 ma v in = 0v, 8 + 33h, v dd = 3.6v 3.8 ma i sd (note 4) sd = gnd 0.2 0.4 a isl99201
4 fn6742.2 november 1, 2013 gain control closed-loop gain d version user program (max gain, ri = 0 ) 27.5 28.5 29.5 db a version 5.7 6 6.3 db b version 9.2 9.6 10 db c version 11.5 12 12.5 db differential input impedance z in sd = v dd , a version 70 k sd = v dd , b version 46.25 k sd = v dd , c version 35 k sd = v dd , d version, ri = 2.5k 7.5 k sd = gnd 100 k shutdown control input voltage high v ih 1.2 v input voltage low v il 0.5 v turn-on time t wu sd rising edge from gnd to v dd 3.5 ms turn-off time t sd sd falling edge from v dd to gnd 5 s output impedance z out sd = gnd >100 k noise performance output voltage noise e n v dd = 3.6v, f = 20hz to 20khz, inputs are ac grounded, a v = 6db, a-weighting 27 v v dd = 3.6v, f = 20hz to 20khz, inputs are ac grounded, a v0 = 6db, no weighting 35 v signal-to-noise ratio snr p out = 1w, r l = 8 102 db notes: 4. limits established by characteri zation and are not production tested 5. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. te mperature limits established by characterization and are not production tested. electrical specifications typical values are tested at v dd = 5v and the ambient temperature at +25c. (continued) parameter symbol test conditions min (note 5) typ max (note 5) units isl99201
5 fn6742.2 november 1, 2013 pin descriptions sd shutdown active low. this signal is used to shut down and activate the part. it is 1.8v to 5v compatible. during shutdown, the part draws less than 100na input current. coming out of shutdown takes 3.5ms and going into shutdown is instantaneous. sync external clock input. this pin allows the chip to be synchronized to a system clock. this helps in folding the spectral components and the switching harmonic out of band of interest. the range of sync frequency is from 250khz to 800khz. in+ positive differential input. in- negative differential input. v o + positive btl output. gnd ground. v dd power supply. v o - negative btl output. block diagram (notes) sawtooth generator shutdown logic over current protection bias and reference click and pop suppression vdd vo- vo+ sd sync 1 in+ in- gnd gate drive with src gate drive with src comp comp vdd vdd +180 + - - + - + + - + - notes: gain = 6db, 9.6db, 12db (gain setting) gain = ; with external resistor 140k (ri + 5k ? ) isl99201
6 fn6742.2 november 1, 2013 typical performance characteristics figure 1. efficiency vs output power figure 2. supply current vs output power figure 3. supply current vs supply voltage figure 4. total harmonic distortion + noise vs output power figure 5. common mode rejection mode vs frequency figure 6. power dissipation vs output power 0 10 20 30 40 50 60 70 80 90 100 0 0.250.500.751.001.251.501.75 efficiency (%) v dd = 2.5 v v dd = 3.6 v r l = 8 + 33h output power (w) v dd = 5 v 0 50 100 150 200 250 300 350 400 0 0.25 0.50 0.75 1.0 1.25 1.50 1.75 output power (w) supply current (ma) v dd = 2.5 v v dd = 3.6 v v dd = 5 v r l = 8 + 33h 2.0 2.5 3.0 3.5 4.0 4.5 5.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 input supply (v) supply current (ma) r l = 8 + 33h r l = no load 0.01 0.10 1 10 100 0.01 0.10 1 10 total harmonic distortion (%) v dd = 5v r l = 8 v dd = 3.6v v dd = 3v v dd = 2.5v output power (w) -100 -90 -80 -70 -60 -50 -40 -30 -20 10 100 1k 10k 100k frequency (hz) cmrr (common mode rejection ratio - db) v dd = 3.6v v ic = 1v p-p r l = 8 isl99201
7 fn6742.2 november 1, 2013 figure 7. power dissipation vs output power figure 8. output power vs supply voltage figure 9. total harmonic distortion + noise vs frequency figure 10. total harmonic distortion + noise vs frequency figure 11. total harmonic distortion + noise vs frequency figure 12. supply ripple rejection ratio vs frequency - isl99201a typical performance characteristics (continued) 0 0.1 0.2 0.3 0.4 0.5 0.6 0 0.25 0.50 0.75 1.00 1.25 1.50 power dissipation (w) output power (w) v dd = 5v r l = 8 f = 1khz gain = 4v/v thd = 10% thd = 1% output power (w) 0.01 0.10 1 10 10 100 1k 10k 100k total harmonic frequency (hz) distortion + noise (%) 0.015w 0.075w 0.2w v dd = 2.5v rl = 8 c l = 2f isl99201a vdd = 2.5v vdd = 3.6v isl99201
8 fn6742.2 november 1, 2013 figure 13. supply ripple rejection ratio vs frequency - isl99201b figure 14. supply ripple rejection ratio vs frequency - isl99201c figure 15. supply ripple rejection ratio vs frequency - isl99201a figure 16. supply ripple rejection ratio vs frequency - isl99201b figure 17. supply ripple rejection ratio vs frequency - isl99201c figure 18. total harmonic distortion + noise vs common mode input voltage typical performance characteristics (continued) -80 -70 -60 -50 -40 -30 10 100 1k 10k 100k frequency (hz) vdd = 5v inputs ac-grounded r l = 8 c l = 2f isl99201b vdd = 2.5v vdd = 3.6v supply ripple rejection ratio (db) -80 -70 -60 -50 -40 -30 10 100 1k 10k 100k frequency (hz) vdd = 5v inputs ac-grounded r l = 8 c l = 2f isl99201c vdd = 2.5v vdd = 3.6v supply ripple rejection ratio (db) -80 -70 -60 -50 40 -30 -20 10 100 1k 10k 100k frequency (hz) v dd = 3.6v inputs floating r l = 8 c l = 2f isl99201a v dd = 5v v dd = 2.5v supply ripple rejection ratio (db) -80 -70 -60 -50 -40 -30 -20 10 100 1k 10k 100k frequency (hz) v dd = 3.6v inputs floating r l = 8 c l = 2f isl99201b v dd = 5v v dd = 2.5v supply ripple rejection ratio (db) -80 -70 -60 -50 -40 -30 -20 10 100 1k 10k 100k frequency (hz) v dd = 3.6v inputs floating r l = 8 c l = 2f isl99201c v dd = 5v v dd = 2.5v supply ripple rejection ratio (db) 0.01 0.1 1 10 0 0.5 1.5 2.5 3.0 3.5 4.5 5.0 total harmonic 5v 3.6v 2.5v 1.0 2.0 4.0 common mode input voltage (v) rejection ratio (%) f = 1khz p o = 200mw isl99201
9 fn6742.2 november 1, 2013 figure 19. supply ripple rejection ratio vs dc common mode voltage figure 20. common mode rejection ratio vs common mode input voltage typical performance characteristics (continued) -70 -60 -50 -40 -30 -20 -10 0 0.25 0.75 1.25 1.75 2.25 2.75 3.25 3.75 4.25 4.75 5.25 supply input rejection ratio (db) dc common mode voltage (v) v dd = 2.5v v dd = 3.6v v dd = 5v -80 -70 -60 -50 -40 -30 -20 -10 0.25 1.25 2.25 3.25 4.25 5.25 common mode 0 rejection ratio (db) common input voltage (v) v dd = 2.5v v dd = 3.6v v dd = 5v typical applications h-bridge power stage and sr control pwm sawtooth generator bias and reference sync v in + v in - sd vo+ vo- v dd gnd differential input c3 ri ri z in ri, rev d z in + - figure 21. typical circuit with differential input h-bridge power stage and sr control pwm sawtooth generator bias and reference sync v in + v in - sd vo+ vo- v dd gnd differential input c3 ri ri z in z in ri, rev d + - figure 22. typical circuit with differential input and input capacitors isl99201
10 fn6742.2 november 1, 2013 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html typical applications (continued) h-bridge power stage and sr control pwm sawtooth generator bias and reference sync v in + v in - sd vo+ vo- v dd gnd differential input c3 c1 c2 ri ri z in ri, rev d + - figure 23. typical circuit with single-ended input c1 = c2 = 1f isl99201
11 fn6742.2 november 1, 2013 isl99201 package outline drawing l8.3x3a 8 lead thin dual flat no-lead plastic package rev 4, 2/10 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.20mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing c onform to asme y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view c 0 . 2 ref 0 . 05 max. 0 . 02 nom. 5 3.00 a b 3.00 (4x) 0.15 6 pin 1 index area pin #1 6x 0.65 1.50 0.10 8 1 8x 0.30 0.10 6 0.75 0.05 see detail "x" 0.08 0.10 c c c ( 2.90 ) (1.50) ( 8 x 0.30) ( 8x 0.50) ( 2.30) ( 1.95) 2.30 0.10 0.10 8x 0.30 0.05 a mc b 4 2x 1.950 (6x 0.65) index area pin 1 compliant to jedec mo-229 weec-2 except for the foot length. 7.

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